TSMC Q1 2026: 58% Profit Jump, 4.17M Wafers, HBM4 Sold Out

TSMC reported a 58% jump in quarterly net profit for Q1 2026 — the largest year-on-year profit acceleration since the AI spending surge began. Record 4.17 million wafers shipped, up 28% year-on-year. The full-year 2026 revenue growth forecast remains above 30%. The underlying driver is not smartphones or PCs. It is HBM4: High Bandwidth Memory generation 4, the component that determines how fast an AI accelerator can move data from memory into compute cores — and every major GPU and custom AI chip for 2026 and 2027 runs on HBM fabricated in partnership with TSMC's advanced packaging lines.

HBM4 is sold out through all of 2026. The HBM total addressable market is projected at $100 billion by 2028, up from approximately $15 billion in 2024. SK Hynix holds 70% of the initial HBM4 allocation. Samsung and Micron are catching up. None of them have inventory to spare.

TSMC Q1 2026: The Numbers

Net profit for Q1 2026 surged 58% year-on-year, reaching approximately NT$400 billion (roughly $12.3 billion USD). This is not TSMC's highest absolute quarterly profit in history — but a 58% acceleration at TSMC's scale in a single quarter reflects a demand curve that is steepening, not leveling off.

The 4.17 million wafers shipped is a record. For context:

• Q1 2024: approximately 3.3 million wafers
• Q1 2025: approximately 3.26 million wafers (softness in consumer electronics)
• Q1 2026: 4.17 million wafers (+28% YoY)

The jump from 2025 to 2026 reflects AI accelerator demand absorbing the slack left by declining smartphone and PC volumes. TSMC's customer mix has shifted: AI chips (custom silicon, GPUs, and networking ASICs) now account for a larger share of advanced node utilization than consumer devices for the first time.

Full-year 2026 revenue growth guidance: greater than 30%. TSMC does not give quarterly guidance by segment, but advanced nodes (3nm and 2nm) are running at effective capacity for AI workloads through at least Q3 2026.

HBM4: What It Is and Why It's Sold Out

High Bandwidth Memory 4 is the memory standard for the next generation of AI accelerators. It stacks DRAM chips vertically (12-16 layers) and connects them to the GPU or AI chip through a silicon interposer — the memory sits next to the compute die rather than on a separate board. The result: memory bandwidth of 1.5-2 TB/s per HBM stack, compared to 900 GB/s for HBM3e.

Why this matters for AI: large language model inference is memory-bandwidth bound, not compute bound, at large batch sizes. A Blackwell Ultra GPU with HBM4 versus HBM3e is not just faster — it can serve more simultaneous inference requests with the same silicon. For data centers paying $2-3 million per GPU cluster, memory bandwidth directly translates to revenue per rack.

HBM4 supply allocation for 2026:

• SK Hynix: approximately 70% of total HBM4 output — primary supplier to Nvidia Blackwell Ultra and custom Google TPU v7
• Samsung: approximately 20%, ramping to close the gap; Samsung's initial HBM4 qualification for Nvidia was delayed in 2025 but is now resolved
• Micron: approximately 10%, growing aggressively; Micron's HBM4 was qualified for Nvidia GB300 and is expanding to other customers

The "sold out through 2026" statement comes from multiple supply chain checks: Rystad Energy, TrendForce, and direct confirmation in SK Hynix's Q1 2026 earnings call (Hynix CEO Kwak Noh-Jung: "HBM demand significantly exceeds our ability to supply through year-end").

OpenAI Titan: TSMC 3nm, Samsung HBM4, Broadcom

The most significant confirmed chip development in the April 29 supply chain reporting: OpenAI's custom AI chip, internally called Titan, is confirmed on TSMC 3nm process with Samsung HBM4 memory and Broadcom as co-development partner.

What Titan is designed to do: replace a portion of the Nvidia H100/H200 clusters that OpenAI currently leases through Microsoft Azure for inference. OpenAI's inference cost is one of its largest operating line items — serving ChatGPT, GPT-5, and API customers costs hundreds of millions of dollars per month in compute. Custom silicon optimized specifically for transformer inference at OpenAI's token volumes could reduce that cost by 30-50%.

The Broadcom co-development is structurally significant. Broadcom is the dominant designer of custom AI ASICs for hyperscalers (Google TPU, Meta MTIA, and now reportedly Apple's inference chip all involve Broadcom engineering). Broadcom brings the packaging expertise and the customer relationships with TSMC's CoWoS advanced packaging lines — the same lines that determine how HBM4 gets stacked onto custom AI dies.

TSMC 3nm for Titan puts OpenAI in the same node as Apple A18, Nvidia Blackwell, and Google Trillium. 3nm is not the most advanced node TSMC ships (2nm N2 production is ramping for late 2026), but 3nm CoWoS with HBM4 is the production-ready combination for shipping at volume in 2026.

Expected production volume: limited. Titan is unlikely to fully replace Nvidia in OpenAI's infrastructure in 2026. The more likely scenario is Titan handles dedicated inference for specific high-volume API workloads (GPT-5 standard tier) while Nvidia GPUs handle training and large-scale burst inference.

Nvidia's HBM Move: Testing 16-Layer Stacks

Nvidia is testing 16-layer HBM stacks for its late 2026 GPU generation — up from 12 layers in current HBM3e deployments. Each additional layer increases memory capacity and bandwidth but adds fabrication complexity.

The 16-layer stack would give Nvidia GPUs approximately 192 GB of HBM per die (at current density). For context: H100 ships with 80 GB HBM3, H200 with 141 GB HBM3e. The jump to 192 GB HBM4 in 16-layer configuration would fundamentally change what LLM inference looks like: models that currently require multi-GPU clusters for inference (GPT-4 class, 70B+ parameter models) could fit on a single GPU.

The bottleneck: TSMC's CoWoS-L and CoWoS-S advanced packaging lines, which bond the HBM stacks to the GPU die, are capacity-constrained through 2026. TSMC has announced a 40% capacity expansion for CoWoS packaging in 2026, but that expansion comes online gradually — it does not solve the Q2-Q3 2026 constraint.

HBM TAM: $100 Billion by 2028

The projected $100 billion HBM total addressable market by 2028 comes from multiple analyst sources (Omdia, TrendForce, Rystad). For context on the magnitude:

• 2024 HBM market: approximately $15 billion
• 2025 HBM market: approximately $35 billion
• 2026 HBM market: approximately $55-60 billion (based on current pricing and volume)
• 2027 projection: $75-80 billion
• 2028 projection: $95-105 billion

The growth is not linear — it reflects a structural shift in data center memory architecture. Standard DRAM (DDR5) is being supplemented and in some workloads replaced by HBM in the memory hierarchy of AI systems. Each generation of AI chip requires more HBM per die.

The supply side cannot keep up with this curve without massive capital investment. SK Hynix alone has committed to $26 billion in 2026 capex, primarily for HBM4 and HBM4E capacity. Samsung and Micron are spending proportionally.

What This Means for Developers

If you deploy AI inference: The compute costs you pay today — for Bedrock, Azure AI, Google Vertex AI — are partly a function of HBM scarcity. When HBM4 supply normalizes (2027-2028), inference pricing will decline structurally, not incrementally. The $630 billion hyperscaler capex cycle being built in 2026 will generate cheap inference compute in 2028. Build architecture that scales with cheaper compute rather than architecture that assumes current pricing is permanent.

If you build AI applications on managed APIs: OpenAI Titan and similar custom silicon projects by Google (TPU v7), Meta (MTIA Gen 3), and Amazon (Trainium 3) are all targeting cost reduction on the inference path you currently pay for. Custom silicon does not create new model capabilities — it reduces the per-token cost of delivering the capabilities that already exist. Your API pricing over the next 24 months will be shaped by how successfully these programs ramp production.

If you plan for GPU access in Azure or AWS: The TSMC CoWoS packaging constraint that limits HBM4 attachment to GPU dies is the same constraint that limits new GPU supply to cloud providers. Azure's supply-constrained 35% growth (see Big Tech earnings above) is downstream of TSMC CoWoS capacity. This resolves gradually through 2026 and more substantively in 2027 as the 40% CoWoS expansion comes online.

Key Takeaways

• TSMC Q1 2026: 58% profit jump: record 4.17M wafers (+28% YoY); full-year 2026 revenue growth >30%; advanced node AI chip demand is the primary driver; 3nm CoWoS-HBM lines running at capacity
• HBM4 sold out through 2026: SK Hynix holds 70% allocation; Samsung and Micron ramping; demand exceeds supply through year-end; every major AI GPU and custom chip for 2026-2027 requires HBM4
• OpenAI Titan on TSMC 3nm: Samsung HBM4, Broadcom co-development; targets inference cost reduction for GPT-5 API workloads; volume limited in 2026 — Nvidia GPU clusters remain primary
• Nvidia testing 16-layer HBM: 192 GB per die configuration; late 2026 target; would enable single-GPU inference for 70B+ parameter models; CoWoS packaging capacity is the binding constraint
• HBM TAM $100B by 2028: up from $15B in 2024; structural shift in data center memory architecture; SK Hynix $26B 2026 capex; Samsung and Micron expanding proportionally
• Developer implication: inference pricing declines structurally in 2027-2028 as HBM4 supply normalizes; current GPU access constraints in Azure/AWS are CoWoS-limited, resolving gradually through 2026

For the Big Tech earnings results that show this compute demand hitting financial results, read Big Tech Q1 2026: Meta +31%, Google Cloud +50%, Amazon Chips $20B. For the SK Hynix HBM demand data confirming sold-out status, read SK Hynix Q1 2026: 71.8% Margin, HBM Orders Eclipse 3-Year Supply. For the TSMC Arizona context, read TSMC Arizona $465B: US-Taiwan Tariff Framework Confirmed.