TSMC 3nm Is Overloaded: Apple, Nvidia, Amazon Fighting for Wafers in 2026

TSMC's 3nm node (N3E and N3P) hit full capacity utilization in March 2026 for the first time since the node entered mass production in late 2023. The constraint is not demand speculation — it's confirmed by multiple customers reporting allocation delays. Apple M5, Nvidia Blackwell GPUs, Amazon Trainium3, and Microsoft Maia 2 are all competing for the same fab slots.

What "3nm Full Capacity" Actually Means

TSMC's N3E process is the primary 3nm variant in volume production. N3P, with improved performance-per-watt, entered production in late 2024. When TSMC hits full utilization on a node, wafer starts are essentially fixed by reactor availability — you cannot add meaningful capacity in less than 18-24 months because adding a new cleanroom fab takes that long.

TSMC currently operates 3nm production at Fab 18 in Tainan across multiple phases. Each phase adds roughly 10,000 to 15,000 wafers per month capacity. Total 3nm capacity is estimated at 100,000-120,000 wafer starts per month across all phases as of Q1 2026. That capacity is now spoken for.

Who Is Taking Up All the Capacity

Apple is TSMC's largest customer by volume and the anchor tenant for 3nm. The M4 chip family — M4, M4 Pro, M4 Max, M4 Ultra — is manufactured on N3E. M5, expected for late 2026, is reportedly on N3P and already consuming allocation. Apple typically locks in 50-60% of a node's total wafer starts during its first two years of production.

Nvidia's Blackwell GPUs — specifically the B200 and the upcoming B300 — use TSMC CoWoS-L packaging with N4P compute dies and N3 memory controller dies. The memory controller die sits on the same node as Apple's M chips. As Nvidia scales Blackwell production to meet cloud provider demand from AWS, Azure, and Google, the 3nm allocation requirements increase.

Amazon Trainium3 and Microsoft Maia 2 are both custom AI accelerators designed on TSMC 3nm. Amazon committed to massive Trainium3 deployments for AWS after strong Trainium2 adoption by Amazon's own ML teams. Microsoft is manufacturing Maia 2 at TSMC after the first generation Maia was produced on TSMC 5nm.

The result is four major customers — Apple, Nvidia, Amazon, Microsoft — each with forecasted demand that exceeds prior quarters, converging on a node that cannot add capacity quickly.

CoWoS Is the Real Bottleneck

The less-discussed constraint is CoWoS (Chip-on-Wafer-on-Substrate) packaging, which TSMC provides alongside wafer production. AI accelerators like Blackwell, Trainium3, and Maia 2 require CoWoS-L to attach HBM memory stacks to compute dies. TSMC's CoWoS capacity has been constrained since 2023 and remains the binding constraint for AI chip production even when wafer capacity is available.

TSMC has been expanding CoWoS capacity aggressively — reportedly doubling it from 2024 to 2025, and planning another 50% increase in 2026. But each CoWoS tool takes 12-18 months to install and qualify. The expansion is happening; it's just slower than demand growth.

What This Means for Cloud GPU Availability

When TSMC can't produce more Blackwell dies, Nvidia can't ship more GPUs, and AWS, Azure, and Google Cloud can't add more B200 instances. The H100 production lines are on older nodes (N4P, 5nm family) and are not capacity-constrained, which is why H100 inventory is relatively stable. H200 production — also on an older node — is similarly unconstrained by 3nm.

The 3nm constraint primarily affects Blackwell GPU supply for the second half of 2026 and Trainium3 rollout at AWS. Developers who need Blackwell-class hardware for training runs in Q3-Q4 2026 are looking at limited availability and premium pricing.

TSMC 2nm Is Not a Near-Term Relief Valve

TSMC's 2nm node (N2) enters risk production in 2025 and volume production in late 2026 with Apple A20 as the first customer. N2 capacity in 2026 is small — perhaps 20,000-30,000 wafer starts per month initially, insufficient to absorb the overflow from N3. N2P, the improved variant, is a 2027 production target.

The practical timeline: 3nm constraints persist through at least mid-2027, when N2 reaches meaningful scale. Until then, AI accelerator supply — Blackwell and its successors — is structurally limited by TSMC's fab expansion pace.

Implications for the Hyperscaler Arms Race

Google, Amazon, and Microsoft are all designing custom silicon partly to reduce dependence on Nvidia and partly to get preferred TSMC allocation outside of Nvidia's purchasing power. That strategy requires them to be TSMC customers themselves, which means they're competing with Nvidia for the same constrained capacity. Custom silicon reduces Nvidia dependence but not TSMC dependence.

The only companies that escape this constraint are those designing chips on non-TSMC nodes — Samsung 3GAE (Gate-All-Around) or Intel 18A. Neither has proven production yields comparable to TSMC N3, which is why no major hyperscaler has committed volume AI production to those nodes.

Key Takeaways

• TSMC 3nm hit full capacity in March 2026 — first time N3E/N3P production is capacity-constrained since launch
• Four major customers competing for allocation: Apple M5 (N3P), Nvidia Blackwell (memory controller die), Amazon Trainium3, Microsoft Maia 2
• CoWoS packaging is the additional bottleneck — AI accelerators need CoWoS-L for HBM attachment, and TSMC CoWoS capacity is expanding slower than AI demand
• Blackwell GPU supply impact: limited B200 instance availability at AWS/Azure/GCP through H2 2026
• H100/H200 are not affected — those chips use older TSMC nodes (N4P, 5nm family) that are not at capacity
• TSMC 2nm won't help until 2027 — N2 volume production begins late 2026 with Apple A20, insufficient scale to offset N3 overflow