China's Dishan Technology Has a 2nm AI Chip Design — But Can't Build It Yet

Shanghai-based startup Dishan Technology has completed prototype verification of a 2nm AI GPU design — a chip that would represent the most advanced AI accelerator designed by a Chinese company if it can be manufactured. The design uses a hybrid FinFET/GAA process architecture with chiplet-based heterogeneous packaging, promising 40% energy efficiency improvement over Dishan's previous generation. There is one problem: no foundry in China can build it at volume, and every foundry that can — TSMC, Samsung, Intel Foundry — is blocked by US export controls from taking Chinese chip orders at this node.

The story of Dishan's 2nm chip is the story of the gap at the center of China's semiconductor strategy: Chinese chip design talent has reached world-class levels, while domestic fabrication capability remains stuck at 7nm-level commercial production. The gap is real, it is documented, and the timeline to close it is measured in years, not months.

What Dishan Technology Built

Dishan was founded in 2021 with an R&D team that includes several IEEE Fellows and researchers from China's national talent programme. The company focuses on high-performance computing chips and sensor chips. The 2nm AI GPU prototype represents their most ambitious project.

The design specifications as reported:

Process node: 2nm, using a hybrid FinFET/GAA (Gate-All-Around) transistor architecture. GAA transistors are the next generation beyond FinFET — TSMC is using a variant called GAAFET in its N2 process, and Samsung introduced MBCFET (a GAA variant) at 3nm. Dishan's hybrid approach may reflect the design team's flexibility around which foundry's process design kit they might eventually use.

Architecture: Chiplet-based heterogeneous design. Rather than a monolithic die, the chip uses multiple smaller dies (chiplets) with different functions assembled together. This is the same approach Nvidia uses in the H100 (compute chiplets plus HBM memory stacks) and AMD uses across its entire product line. Chiplet designs are more tolerant of yield issues — a bad compute chiplet does not waste the I/O and memory chiplets assembled with it.

Performance: The 40% energy efficiency improvement claim is relative to Dishan's previous generation, not to Nvidia or Huawei benchmarks. Without independent testing of a fabricated chip, this figure is a design simulation estimate.

Status: Prototype verification — this means the design has been validated in simulation and on FPGA (field-programmable gate array) emulation platforms. The chip design file is complete enough that it could theoretically be sent to a foundry for tape-out. It has not been taped out or manufactured.

The Foundry Problem: Why a Design Without a Factory Is a Paper Chip

A chip design without a foundry to manufacture it is not a chip. It is a CAD file. The foundry problem is the central fact of Dishan's situation and the central fact of China's 2nm ambitions.

TSMC: Manufactures 2nm (N2 process, entering volume production in 2025). Blocked by US export controls from taking orders from Chinese chip designers for advanced nodes (typically defined as below 16nm for logic). TSMC has terminated existing relationships with Chinese advanced-node customers under BIS pressure. Not available to Dishan.

Samsung Foundry: Has 2nm-class GAA process (3nm GAA in production, 2nm in development). Also subject to US export control restrictions that prevent manufacturing for Chinese companies at advanced nodes. Not available.

Intel Foundry: Intel 18A process (approximately 1.8nm-class). US domestic manufacturer under even stricter restrictions on Chinese customers. Not available.

SMIC: China's largest domestic foundry. Currently produces at 7nm using DUVi multi-patterning (as documented in the AEI lithography loophole report). SMIC's 5nm capability is in limited yield development. SMIC has no demonstrated 2nm or 3nm process. The timeline for SMIC to develop a 2nm process — assuming access to advanced EUV tools, which ASML cannot export to China — is estimated at 5-10 years minimum by most industry analysts. Not available at any timeline close to Dishan's needs.

Other Chinese foundries (Hua Hong, CXMT): Operate at even more mature nodes (28nm-90nm for Hua Hong, DRAM-focused for CXMT). Not relevant for leading-edge logic.

Dishan's publicly stated timeline — pre-tapeout verification complete by end 2025, mass production Q1 2026 — has already slipped significantly. TrendForce reported in April 2026 that the chip has not yet entered the tapeout stage. The revised realistic timeline for volume production is 2027-2028 at the earliest, contingent on a fabrication solution that does not currently exist.

Why This Story Matters Despite the Manufacturing Gap

The honest read on Dishan's 2nm chip is: China can design it, China cannot build it, and the gap between those two facts is where US export controls are currently winning.

But the design capability itself is significant for four reasons:

Talent signal: A team that can design a 2nm AI GPU is competitive with design teams at AMD, Nvidia, Qualcomm, and Apple. The design discipline required for FinFET/GAA hybrid processes at 2nm involves process design kit mastery, parasitic extraction, timing closure, and power analysis at a level that did not exist in Chinese design houses five years ago. The talent pipeline is building from the bottom up.

Process agnosticism: The hybrid FinFET/GAA architecture suggests Dishan is designing for multiple possible foundry relationships. If SMIC develops a near-2nm process (even if it is technically 3nm by SMIC's internal naming), or if geopolitical conditions change enough for a third-country foundry to take Dishan's order, the chip design is ready. The CAD file does not expire.

Leverage for policy: Chinese government officials can point to Dishan's design capability when arguing that domestic chip development deserves more investment. A validated 2nm design demonstrates that the constraint is manufacturing, not engineering — which is a solvable industrial policy problem, not a fundamental capability gap.

The SMIC 5nm precedent: SMIC's 7nm demonstration was dismissed as impossible by Western analysts until it appeared in production Huawei chips. SMIC's 5nm development is currently at low yield. The transition from "impossible" to "happening" in Chinese chip manufacturing has consistently arrived faster than Western consensus predicted. Dishan's design may be waiting for SMIC to close the manufacturing gap rather than the other way around.

How This Connects to the Huawei 950PR

Dishan and Huawei are solving the same problem from different angles. Huawei's Ascend 950PR is a chip that can be manufactured at scale today (SMIC 7nm), optimised for the current production constraint. Dishan's 2nm design is targeting the frontier node that would be needed to compete with Nvidia's H100/H200-class performance.

The current Chinese AI chip stack (Ascend 950PR for production, Dishan 2nm for the research frontier) mirrors the US stack circa 2018-2019: commercially competitive chips available now, next-generation designs being validated for future production. The gap between the Chinese 2026 stack and the Nvidia 2026 stack (B200, GB200) is roughly three generations of process node advantage — real, significant, but not unbridgeable on a 5-10 year horizon.

Developer Implications

For developers evaluating Chinese AI chips today: Dishan's 2nm chip is not a product you can buy or deploy. The Huawei Ascend 950PR is. Do not conflate the two — one is a production chip with confirmed orders and manufacturing, the other is a design awaiting fabrication infrastructure.

For developers tracking the China chip trajectory: The fabrication gap is the key metric to watch. SMIC's progress toward 5nm (which would unlock production of near-leading-edge Chinese chip designs) is the single most important indicator of when Chinese domestic chips can match Nvidia performance at frontier nodes.

For developers doing export control risk assessment: The Dishan situation shows exactly what US export controls are accomplishing — the design gap has closed, but the manufacturing gap remains. Policy interventions targeting EDA tools, foundry access, and advanced packaging are more effective at maintaining the manufacturing gap than chip-level export controls alone.

Key Takeaways

• Dishan 2nm prototype verified: Shanghai startup, founded 2021, IEEE Fellows team; hybrid FinFET/GAA chiplet design; 40% energy efficiency improvement claimed
• Cannot be manufactured in China: TSMC/Samsung/Intel blocked by export controls; SMIC maximum 7nm commercial production; Dishan timeline slipped — now 2027-2028 at earliest for volume production
• Design-manufacturing gap is the export control win: China can design 2nm AI chips; China cannot build them; that gap is what US controls are currently enforcing
• Chiplet-based design is foundry-agnostic: ready for whichever manufacturing path becomes available first — SMIC 5nm, third-country foundry, or policy change
• Contrast with 950PR: Ascend 950PR is a production chip you can buy today (SMIC 7nm); Dishan 2nm is a future chip without a factory — do not conflate them
• Watch SMIC 5nm progress: the fabrication gap metric that determines when Chinese frontier chip designs become producible products

For the Huawei 950PR that is in production now, read Huawei Ascend 950PR: ByteDance $5.6B Order, CUDA-Compatible. For the SMIC manufacturing capability that enables current Chinese chips, read China's DUV Lithography Loophole: SMIC Near-Frontier Chips. For India's parallel semiconductor buildout at different process nodes, read India Semiconductor Mission 2.0: Tata First Silicon, Micron ATMP Open.