Japan Is Spending $67 Billion to Rebuild Its Chip Industry in 10 Years

Japan is committing roughly $67 billion over 10 years to rebuild its semiconductor industry. The plan includes Rapidus, the state-backed logic fab targeting 2 nm in Hokkaido, and the already operational TSMC Kumamoto plant (with a second fab under construction for 3 nm). Japan dominated chips in the 1980s, lost ground to Taiwan and South Korea, and is now making its largest push to return. By 2030 the goal is a real share of advanced logic production, not just materials and equipment.

Why Japan Is Spending So Much

Japan once led in memory and logic. Then Taiwan (TSMC) and South Korea (Samsung, SK Hynix) took the lead. Today almost all advanced logic is made in Taiwan and South Korea. Japan wants a share of that again for economic and supply chain security reasons. The $67 billion is the stated envelope for the next decade: subsidies for fabs, equipment, and R&D. The bet is that in a world of geopolitical and concentration risk, a third hub for advanced logic is worth the cost.

Rapidus is the flagship. It is the Japanese company set up to build and run advanced logic fabs with government backing. The goal is 2 nm and beyond. TSMC Kumamoto is different: it is a TSMC-owned fab on Japanese soil, already producing. That gives Japan immediate capacity and technology transfer while Rapidus aims for the frontier.

What Is Already Running: TSMC Kumamoto

TSMC first Kumamoto fab began mass production of 12 to 28 nm chips in December 2024. It is one of the first major TSMC fabs outside Taiwan. The Japanese government provided substantial subsidies. A second Kumamoto fab is under construction: TSMC announced plans to upgrade it to produce advanced 3 nm chips (a step up from the initially planned 6 nm). The investment for the second plant is on the order of $13.9 billion, with Japanese government subsidies of up to 732 billion yen (about $4.7 billion). For the global supply chain, that means more geographic diversity and a real non-Taiwan source for mature and advanced nodes. For developers and infrastructure teams, the chips that end up in servers and devices may increasingly have a Japanese manufacturing step.

What Rapidus Is For: 2 nm and the 2030 Target

Rapidus is meant to restore Japanese capability at the leading edge. It is not just packaging or mature nodes; the ambition is 2 nm. The company has a pilot line in Chitose, Hokkaido (IIM, Innovative Integration for Manufacturing), and in July 2025 it successfully prototyped 2 nm GAA (Gate All Around) transistors there. The target is mass production of 2 nm in the second half of fiscal 2027, with full-scale production by fiscal 2028. Rapidus has publicly said it expects a 2 nm supply shortfall by 2030 and is working on talent and capacity to fill that gap. The 2030 target is aggressive; if Rapidus hits its goals, Japan would again be a producer of advanced logic, not only a supplier of materials and equipment.

What This Means for the Global Supply Chain and Developers

More capacity in Japan reduces reliance on Taiwan and South Korea for the final fabrication step. It does not replace them overnight. But over 5 to 10 years, a successful Japanese revival would mean three major geographic hubs for advanced logic: Taiwan, South Korea, and Japan. That would matter for resilience and for anyone planning long-term hardware dependency.

For developers, the impact is indirect. You do not buy from Rapidus or TSMC directly. You buy from system vendors and cloud providers. The takeaway is that the industry is betting on Japan again. Supply chain and procurement discussions will increasingly include Japanese capacity in the picture. If you care about where your chips are made (for compliance, risk, or diversification), Japan is back in the map.

Key Takeaways

• $67 billion: Japan's stated 10-year budget for semiconductor revival
• TSMC Kumamoto: first fab producing 12 to 28 nm since Dec 2024; second fab under construction for 3 nm (about $13.9B investment, up to 732B yen subsidy)
• Rapidus: 2 nm pilot in Chitose, Hokkaido; mass production target 2H FY2027, full-scale by FY2028; expects 2 nm supply shortfall by 2030
• For developers: Chip supply will gradually reflect more Japanese capacity; plan for a multi-hub logic supply chain over the next 5 to 10 years
• What to watch: Rapidus 2 nm ramp and TSMC Kumamoto second fab 3 nm timeline through 2026 and 2027